Clock division chip for computer system which interfaces a slower cache memory controller to be used with a faster processor

摘要

A clocking control circuit for a computer system and method for receiving a microprocessor clock signal which drives a microprocessor and for supplying a support clock signal having a lower frequency. The support clock frequency drives support interface circuitry such as a peripheral controller, a CPU/memory controller, and a bus bridge interface, and thus causes the support interface circuitry to operate at a lower frequency than the microprocessor. The clocking control circuit ensures synchronization between the support clocking signal and the microprocessor clocking signal. The transmission of control signals between the microprocessor and support interface circuitry is controlled to ensure proper communications between the microprocessor and support circuitry.