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MANUFACTURE OF N-CHANNEL AND P-CHANNEL JUNCTION FIELD-EFFECT TRANSISTOR AND CMOS TRANSISTOR BY USING CMOS OR BIPOLAR/CMOS MANUFACTURE

机译:使用CMOS或双极/ CMOS制造N沟道和P沟道结型场效应晶体管和CMOS晶体管

摘要

PURPOSE: To provide a junction-type field effect transistor(FET) with a stable threshold voltage by adding the alteration of a mask, two masks, and an etching process to CMOS manufacturing method. CONSTITUTION: A mask of a 4th process demarcates an active region 51 of a JFET 5, according to processes of MOS transistors(TR) 1 and 3, a mask of a 7th process demarcates a source 35 and a drain 37 in it, and N-type impurities are implanted in the source 31 and drain 33 of the N-channel MOS TR 3 at the same time. In an additional process, a gate oxidized film is removed from an active region 15 of the JFET 5, impurities are implanted in an exposed region demarcated by a field oxidized film 21 to form a channel region 19 of the JFET 5, and a mask of an 8th process demarcates a substrate contact 45 surrounding the gate 43 and drain 37. Therefore, a mask of a final process is provided with a metal contact at the electrode of the JFET 5, which is made to cope with a passivation film, so that a JFET with a stable threshold voltage can be obtained.
机译:目的:通过向CMOS制造方法中增加掩模,两个掩模和蚀刻工艺的变化,提供具有稳定阈值电压的结型场效应晶体管(FET)。组成:第四工艺的掩模划定了JFET 5的有源区51,根据MOS晶体管TR和3的工艺,第七工艺的掩模划定了其中的源极35和漏极37,N型杂质被同时注入到N沟道MOS TR 3的源极31和漏极33中。在另一过程中,从JFET 5的有源区15去除栅极氧化膜,将杂质注入到由场氧化膜21划界的暴露区域中,以形成JFET 5的沟道区19和掩模。第八工艺划定了围绕栅极43和漏极37的衬底接触45。因此,最后工艺的掩模在JFET 5的电极处设置有金属接触,该金属接触被制成以应对钝化膜,从而可以获得具有稳定阈值电压的JFET。

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