VERIFICATION SUFFICIENCY EVALUATING SYSTEM FOR SOFTWARE DESIGN SPECIFICATION

摘要

PURPOSE:To verify and evaluate whether design specification is suitable or not by analyzing the design specification prepared on the stage of design, simulating it, and calculating the degree of covering the design specification. CONSTITUTION:A mechanism for evaluating the verification sufficiency of the design specification for the software of real-time control is composed of a picture control part 6, input analysis part 7 for generating the design specification such as a state transition table or a task specification as the start trigger of simulation execution from pictures, simulation execution part 9 to simulate the transition and execution of states according to the contents of the design specification, coverage rate calculation part 12 to calculate the degree of covering the design specification by analyzing the result, and display/editing part 13 to display/output the calculated result on the specification. Thus, the design specification can be efficiently confirmed and the confirmation miss can be prevented by evaluating the verification sufficiency with the degree of coverage corresponding to the design specification on the stage of design.