DATABUS PARITY AND HIGH SPEED NORMALIZATION CIRCUIT FOR A MASSIVELY PARALLEL PROCESSING SYSTEM

摘要

A processing array including a plurality of processing elements; and an interconnection network connected to all of the processing elements, wherein each of the processing elements includes a parity generating circuit for generating a parity bit for a first data message that is transmitted by that processing element to another processing element; and a separate parity circuit for checking parity of a second data message as it is received by that processing element over the interconnection network. Each processing element includes a shift register capable of storing an N-bit number; shifter control circuitry connected to the shift register for causing the shift register to shift the N-bit number in a preselected direction m bits at a time (m1, N=m), and detection circuitry connected to the shift register, the detection circuitry monitoring the m most significant bits of data stored in the shift register and asserting a non-zero detect signal when any of the m most significant bits is a non-zero bit, wherein the shifter conttrol circuitry receives the asserted non-zero detect signal and responds to it by disabling shifting.