DATABUS PARITY AND HIGH SPEED NORMALIZATION CIRCUIT FOR A MASSIVELY PARALLEL PROCESSING SYSTEM

摘要

The described system includes: a processing matrix composed of a plurality of processing elements; and an interconnection network connected to all processing elements, each of which contains a parity generating circuit for generating a parity bit for a first data message that is transmitted by a first processing element to a second processing element ; and a separate parity check circuit which checks the parity of a second data message at the time of its receipt by the first processing element over the interconnection network. Each of the processing elements includes a shift register capable of storing a number of N bits; a shifter control circuitry connected to the shift register and allowing the latter to shift the N-bit number in a preselected direction over a distance of m bits at a time (m 1, N = m); and a detection circuit connected to the shift register circuitry that monitors the most significant m bits of data stored in the shift register and which requires a different detection signal of zero when one m-bit weight Box is a zero bit. Shifter control circuit then receives the detection signal different from zero which has been imposed and responds by disabling the offset function.