DATABUS PARITY AND HIGH SPEED NORMALIZATION CIRCUIT FOR A MASSIVELY PARALLEL PROCESSING SYSTEM

摘要

the system described includes a matrix composed of a plurality of processing elements for processing; and a grid is connected to all of the processing elements.each of which contains a parity generator circuit used to generate a parity bit to a first data message which is transmitted from a first component to a second component of treatment treatment; and a parity check circuit separately.the parity of a second control message data when received by the first processing element in the interconnection network.each of the processing elements includes a shift register capable of storing a number of n bits, and a control circuit connected to the shift register du00e9caleur, and enabling it to change the number of n bits in a preselected direction over a distance. bits at a time (m 1, n = m); and a detection circuit connected to the shift register.a circuit monitors the weight of m bit data stored in the shift register, and a detection signal is not zero when one of the m bits of a bit weight is non-zero. the control circuit receives the detection signal du00e9caleur is different from zero, which was imposed and invalidating function is off.