Programm controlled optimization of a processor controlled circuit for producing an algorithmically generatable data output sequence

摘要

A computer program controlled method/arrangement for automatically configuring a processor-controlled circuit for generating an output sequence of values. This output sequence can preferably represent an address sequence as required for addressing memory products to be tested or logic circuits to be tested. The basis for this method is that an algorithmically generatable output sequence of values C1; C2; C3; C4 is split into imaginary p part-sequences (S1; S2; S3; ....) with in each case associated algorithms. The algorithm A1; A2; A3; A4; etc. of the output sequence exhibits a period of p values. The part-sequences (e.g. S1) can be generated from their starting value and their algorithm as11; as12; as13; etc. All part-sequences can be combined by multiplexing to form the output sequence. In the optimisation case, all values of the part-sequence algorithms consist of a single constant (or of a single mathematically describable term), which leads to great simplifications in the implementation of a circuit: to generate each part-sequence, one processor is required in each case as in a normal case but only a single program memory is required for the constant (or the mathematically describable term). Each processor generates this part-sequence from this constant and the initial value of the associated part-sequence; all part-sequences are combined via a multiplexer to form the desired output sequence. When fewer than p part-sequences are formed, the method requires fewer processors but, instead, a single program memory (93) for predetermining the values of the part-sequence algorithm period if this period is the same in all part-sequence algorithms. This program memory is preferably a register circuit for positive or negative constants, which also takes into consideration mutual displacements of the period in the part-sequence algorithms. The method enables, inter alia, the testing of future fast memory products etc. to be carried out and the complexity of existing test systems to be simplified. To increase the speed of the output sequence, a special embodiment of the processors is provided. It is used for eliminating the time delays occurring in the formation of carries in successive arithmetic operations. IMAGE