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High-definition TV's rounding circuit

机译:高清电视的四舍五入电路

摘要

The present invention relates to a signal processing technique of a high definition television (HDTV). In signal processing of a high definition television (HDTV), dividing a dividend by divisor is performed and the remaining state is examined to add 1 or-1 to the quotient In this case, when the dividend is 16-bit data, there is a problem in that it takes a considerable delay time to perform addition and division even when designing as a general TTL. In order to solve this problem, the present invention is not limited to positive and negative values, The state of the bit is detected and rounded, and the adder is composed of the AND gate and the EXCLUSIVE O gate, thereby improving the processing speed.
机译:高清晰度电视(HDTV)的信号处理技术领域本发明涉及高清晰度电视(HDTV)的信号处理技术。在高清晰度电视(HDTV)的信号处理中,执行除数除以除数,然后检查剩余状态以将1或-1加到商中。在这种情况下,当除数为16位数据时,问题在于,即使设计为通用TTL,也需要相当长的延迟时间来执行加法和除法。为了解决该问题,本发明不限于正值和负值,位的状态被检测和舍入,并且加法器由与门和排他性O门组成,从而提高了处理速度。

著录项

  • 公开/公告号KR940019151A

    专利类型

  • 公开/公告日1994-08-19

    原文格式PDF

  • 申请/专利权人 이헌조;

    申请/专利号KR19930001261

  • 发明设计人 김시중;

    申请日1993-01-30

  • 分类号H04N7/12;

  • 国家 KR

  • 入库时间 2022-08-22 04:37:33

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