The present invention relates to a signal processing technique of a high definition television (HDTV). In signal processing of a high definition television (HDTV), dividing a dividend by divisor is performed and the remaining state is examined to add 1 or-1 to the quotient In this case, when the dividend is 16-bit data, there is a problem in that it takes a considerable delay time to perform addition and division even when designing as a general TTL. In order to solve this problem, the present invention is not limited to positive and negative values, The state of the bit is detected and rounded, and the adder is composed of the AND gate and the EXCLUSIVE O gate, thereby improving the processing speed.
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