Switching output clock signal between two async. input pulse signals - switching between input clock signals triggered by switching signal sync. with rising edge of output signal

摘要

The clock switching method switches between two asynchronous input clock signals (AC, BC). Switching between clock signals is triggered by a switching signal (C) which is synchronous with the rising edge of the actual output clock signal (RC). A hold state of the output signal corresponding to a logical "1" state follows the rising edge of the clock. The hold state is cancelled on the first rising edge of the input clock signal which is being switched through. ADVANTAGE - Requires only one signal for switching between input clock signals.