Slave controller utilizing eight least/most significant bits for accessing sixteen bit data words

摘要

A slave controller which provides the control signals for effecting the r and write operation of a memory electrically connected to the VERSA MODULE EUROPE bus (VMEbus). The slave controller comprises a programmable array logic device which receives control and address modifier signals from the data transfer bus within the VMEbus and an address enable signal from a decoding circuit. The decoding circuit, in turn, provides the address enable signal to the programmable array logic device in response to an address strobe signal supplied to the decoding circuit by the data transfer bus. The programmable array logic device being responsive to the control, address modifier and address enable signals enables the memory which for a read or write operation. The programmable array logic device next provides a write pulse to the memory when data is to be written into the memory at an address provided by the VMEbus. When data is to be read from the memory, programmable array logic device maintains the memory's write enable input at an inactive state and generates an output enable pulse allowing data to be read from the memory at an address provided by the VMEbus. Directional control of data between the memory and the VMEbus for the read and write operations is provided by a pair of transceivers.