首页> 外国专利> Method of doping gate electrodes discretely with either P-type or N-type impurities to form discrete semiconductor regions

Method of doping gate electrodes discretely with either P-type or N-type impurities to form discrete semiconductor regions

机译:用p型或n型杂质离散掺杂栅电极以形成离散半导体区域的方法

摘要

The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N- type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region. The masking layer is removed from the second semiconductor region and a masking layer is formed on the first semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The second semiconductor region is doped with an impurity of P-type, thereby forming a fourth semiconductor region in the second semiconductor region. By providing a masking layer to fall between the end portions of the gate electrodes, the gate electrodes are discretely doped to form discrete semiconductor regions.
机译:半导体器件的制造方法技术领域本发明涉及一种半导体器件的制造方法。在形成有P型的第一半导体区域和N型的第二半导体区域以及形成在第一和第二半导体区域之间并延伸到第一和第二半导体区域之间的绝缘膜的半导体基板中,多晶硅层和层叠体的栅电极形成为栅电极。在覆盖第一和第二半导体区域的绝缘膜上形成硅化物层。位于第一半导体区域上的栅电极的端部面对并且与位于第二半导体区域上的栅电极的端部隔开。掩模层形成在第二半导体区域上,掩模层的边缘落在两个栅电极之间,其中两个端部彼此面对。第一半导体区域掺杂有N型杂质,从而在第一半导体区域中形成第三半导体区域。从第二半导体区域去除掩模层,并且在第一半导体区域上形成掩模层,其中掩模层的边缘落在两个栅极电极之间,其中两个端部部分彼此面对。第二半导体区域掺杂有P型杂质,从而在第二半导体区域中形成第四半导体区域。通过提供掩膜层以落入栅电极的端部之间,栅电极被离散地掺杂以形成离散的半导体区域。

著录项

  • 公开/公告号US5328864A

    专利类型

  • 公开/公告日1994-07-12

    原文格式PDF

  • 申请/专利权人 HITACHI LTD.;

    申请/专利号US19910699024

  • 发明设计人 SATOSHI KUDO;KEIICHI YOSHIZUMI;

    申请日1991-05-13

  • 分类号H01L21/336;

  • 国家 US

  • 入库时间 2022-08-22 04:31:29

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