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Testability architecture and techniques for programmable interconnect architecture

机译:可测试性架构和可编程互连架构技术

摘要

In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with the first conductor, and a plurality of antifuses connected between the first conductor and the second conductors at the intersections, a method for testing the integrity of the plurality of antifuses after attempting to program a selected one of the antifuses, including the steps of precharging each of the second conductors to a first preselected voltage potential such that a selected dynamic voltage is placed on each of the second conductors; placing a second voltage potential on the first conductor, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of the second conductors.
机译:在一种集成电路中,一种用于测试完整性的方法,该集成电路包括沿第一方向布置的第一导体,与第一导体形成交叉点的多个第二导体以及在该交叉点处连接在第一导体和第二导体之间的多个反熔丝。在尝试对一个反熔丝中的一个进行编程之后,选择多个反熔丝中的一个,包括以下步骤:将每个第二导体预充电到第一预选电压电势,以便将选定的动态电压放置在每个第二导体上;在第一导体上放置第二电压电势,其中第一电压电势和第二电压电势之差小于引起良好的反熔丝退化所需的电压;等待预选的时间;并感测每个第二导体上的电势。

著录项

  • 公开/公告号US5341092A

    专利类型

  • 公开/公告日1994-08-23

    原文格式PDF

  • 申请/专利权人 ACTEL CORPORATION;

    申请/专利号US19920958879

  • 发明设计人 JIA-HWANG CHANG;KHALED A. EL-AYAT;

    申请日1992-10-07

  • 分类号G01R31/02;

  • 国家 US

  • 入库时间 2022-08-22 04:31:15

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