Pipelined system for decomposing instruction into two decoding parts and either concurrently generating two operands addresses of merging decomposing decoding codes based upon the second operand

摘要

A pipelined data processor decomposes an instruction into a plurality of processing units (step codes), each corresponding to an operand of the instruction. In the register direct addressing mode, where the source operand of the instruction is an immediate value and the destination operand of the instruction is a register, the data processor combines the two step codes associated with the two operands into one. Thus, the number of cycles required for processing the instruction is reduced.