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ACCELERATED LIFE TESTING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

机译:半导体集成电路的加速寿命测试方法

摘要

PURPOSE: To provide an accelerated life testing method of a semiconductor integrated circuit wherein the method can surely prevent thermal destruction of a circuit element attributed to a latch-up phenomenon and set the heating temperature and the applied voltage to be sufficiently high. ;CONSTITUTION: At the time of a dynamic burn-in screening carried out while bias being applied to an electric power source voltage E and a signal voltage S at temperature as high as 125°C, resetting to set the electric power source voltage E and the signal voltage S at low level periodically in a cycle is repeated wherein the cycle is regulated by the electrification time T within which element destruction does not occur even if a latch-up phenomenon happens and a reset time (t) in which the latch-up current is surely shut off.;COPYRIGHT: (C)1995,JPO
机译:目的:提供一种半导体集成电路的加速寿命测试方法,其中该方法能够可靠地防止归因于闩锁现象的电路元件的热破坏,并将加热温度和施加电压设置得足够高。 ;构成:在动态老化筛选时,在高达125°C的温度下对电源电压E和信号电压S施加偏置时,复位以设置电源电压E和在一个周期中周期性地重复低电平的信号电压S,其中该周期由通电时间T调节,在通电时间内,即使发生闩锁现象也不会发生元件损坏,并且在复位时间(t)中,上升电流肯定被切断。;版权所有:(C)1995,日本特许厅

著录项

  • 公开/公告号JPH07174816A

    专利类型

  • 公开/公告日1995-07-14

    原文格式PDF

  • 申请/专利权人 KAWASAKI STEEL CORP;

    申请/专利号JP19930319385

  • 发明设计人 HAMAGISHI KENJI;

    申请日1993-12-20

  • 分类号G01R31/26;G01R31/28;H01L21/66;

  • 国家 JP

  • 入库时间 2022-08-22 04:28:17

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