SIMULATION DEVICE FOR LOGIC CIRCUIT AND COMPILING METHOD FOR FUNCTION DESCRIBING LANGUAGE OF LOGIC CIRCUIT

摘要

PURPOSE: To provide a simulation device for logic circuits that can decrease the number of tables where the arithmetic results are previously stored and also can reduce the size of each table. ;CONSTITUTION: This simulation device is provided with a hardware description language(HDL) describing/analyzing part 11 which analyzes the HDL describing the function of a logic circuit to be simulated and extracts the operator string of each sentence, a merge deciding part 13 which decides the propriety of sharing of each operator string based on the operator string obtained at the part 11 for each sentence, an arithmetic code generating part 14 which generates an arithmetic code that is capable of simulation based on the deciding result of the part 13, and a table producing part 16 which produces a table that performs an arithmetic operation based on the arithmetic code generated at the part 14 and stores this arithmetic result.;COPYRIGHT: (C)1995,JPO