首页> 外国专利> DELAY TIME CALCULATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND COMPUTER AIDED DESIGN DEVICE

DELAY TIME CALCULATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND COMPUTER AIDED DESIGN DEVICE

机译:半导体集成电路与计算机辅助设计装置的延时计算方法

摘要

PURPOSE: To accurately calculate the delay time of a logic cell without the need of calculating a delay time equation. ;CONSTITUTION: Delay time by the rounding of an input signal for deciding the delay time of the logic cell, load capacity and plural pieces of information of delay time corresponding to them are defined in a delay definition file 3. A delay time calculation device 12 reads information of the logic cell developed from a data base 2 and information of a net, allocates load capacity on the respective nets and calculates the input slews of the logic cell. The calculation device 12 calculates the delay time of the respective logic cells by an interpolation method based on the input slews of the logic cell whose delay time is to be calculated, the load capacity of an output terminal, the input slews of the respective logic cells, the load capacity of the output terminal and delay time corresponding to them, which are stored in the file 3.;COPYRIGHT: (C)1995,JPO
机译:目的:无需计算延迟时间方程即可准确计算逻辑单元的延迟时间。 ;组成:通过舍入用于确定逻辑单元的延迟时间的输入信号的延迟时间,在延迟定义文件3中定义了负载容量和与其对应的多个延迟时间信息。延迟时间计算装置12读取从数据库2开发的逻辑单元的信息和网络的信息,在各个网络上分配负载容量,并计算逻辑单元的输入摆率。计算装置12基于要计算其延迟时间的逻辑单元的输入摆率,输出端子的负载容量,各逻辑单元的输入摆率,通过插值法,求出各逻辑单元的延迟时间。 ,输出端子的负载能力和与其对应的延迟时间,都存储在文件3中; COPYRIGHT:(C)1995,JPO

著录项

  • 公开/公告号JPH07296017A

    专利类型

  • 公开/公告日1995-11-10

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;FUJITSU VLSI LTD;

    申请/专利号JP19940088920

  • 发明设计人 HORIE SHINJI;

    申请日1994-04-26

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 04:22:55

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