首页> 外国专利> TIMING MODEL AND CHARACTERIZATION SYSTEM FOR LOGIC SIMULATION OF INTEGRATED CIRCUITS WHICH TAKES INTO ACCOUNT PROCESS, TEMPERATURE AND POWER SUPPLY VARIATIONS

TIMING MODEL AND CHARACTERIZATION SYSTEM FOR LOGIC SIMULATION OF INTEGRATED CIRCUITS WHICH TAKES INTO ACCOUNT PROCESS, TEMPERATURE AND POWER SUPPLY VARIATIONS

机译:考虑帐户过程,温度和电源变化的集成电路逻辑仿真的优化模型和特征系统

摘要

A method determines approximate propagation delay through logic cells (30, 31) within a library. Each logic cell (30) within the library is characterized at baseline conditions to obtain parameters for each logic cell (30) which define propagation delay through each logic cell (30) at the baseline conditions. A subset of the logic cells (30) are characterized at conditions varying from the baseline conditions to obtain scaling parameters. The scaling parameters modify values of the parameters for all logic cells (30) within the library in order to approximate changes in propagation delay through each logic cell (30) resulting from changes in the baseline conditions. In the preferred embodiment, the conditions varying from the baseline conditions includes a change in at least one of operating temperature, power supply voltage and process conditions.
机译:一种方法确定通过库内的逻辑单元(30、31)的近似传播延迟。库中的每个逻辑单元(30)在基线条件下被表征以获得每个逻辑单元(30)的参数,这些参数定义了在基线条件下通过每个逻辑单元(30)的传播延迟。在不同于基线条件的条件下表征逻辑单元(30)的子集以获得缩放参数。定标参数修改库内所有逻辑单元(30)的参数值,以便近似于由基线条件的变化导致的通过每个逻辑单元(30)的传播延迟的变化。在优选实施例中,不同于基线条件的条件包括工作温度,电源电压和工艺条件中至少之一的变化。

著录项

  • 公开/公告号WO9526533A1

    专利类型

  • 公开/公告日1995-10-05

    原文格式PDF

  • 申请/专利权人 VLSI TECHNOLOGY INC.;

    申请/专利号WO1994US14968

  • 发明设计人 MISHELOFF MICHAEL NORMAN;

    申请日1994-12-27

  • 分类号G06F17/50;

  • 国家 WO

  • 入库时间 2022-08-22 04:14:28

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