Process for manufacturing silicon-germanium bipolar heterojunction transistors

摘要

A process is described for fabricating integrated silicon-germanium bipolar heterojunction transistors comprising a silicon collector layer, a silicon-germanium base layer, a silicon emitter layer and a silicon emitter connection layer. The following process steps are scheduled: a) collector layer, base layer, emitter layer and emitter connection layer are deposited by means of a single, uninterrupted process and at the same time are doped, b) to the side of the base layer, a base connection zone is formed in such a way that the planes of intersection of the base-emitter-PN boundary layer and of the base-collector-PN boundary layer with the surface of the semiconductor arrangement are outside the silicon-germanium base layer, c) on the entire exposed silicon surface of the semiconductor arrangement a silicon dioxide layer is formed by thermal oxidation. IMAGE