Test circuit for reliability test of chip and semiconductor memory device having the test circuit

摘要

The present invention relates to a test circuit for shortening the time required for testing a semiconductor memory device, particularly for a reliability of a chip, and a test circuit of the semiconductor memory device according to the present invention is connected to a bit line, A bit line level sensing circuit for controlling the driving of the bit line level sensing circuit, a bit line level sensing circuit for sensing the bit line level sensing circuit, And transfer means for transferring the data transferred from the circuit to the outside of the chip, wherein the test circuit tests whether the memory cell is defective or not through the column gate. The test circuit of the semiconductor memory device according to the present invention described above has disclosed a technique for testing without passing through the column gate. The test circuit of the semiconductor memory device according to the present invention makes it possible to test whether each memory cell is defective through the bit line without passing through the column gate, /RTI Also, memory cell test can be performed at high speed irrespective of the number of data input / output lines. This test circuit ultimately has the effect of significantly shortening the test time of the semiconductor memory device.