Self-Disable Power-Up Detection Circuit (SELT-DISABLING POWER-UP DETECTION CIRCUTT)

摘要

The CMOS power-up reset circuit provides a power-up output signal useful for an external circuit when the applied power supply voltage exceeds a first predetermined value, wherein the power-up and the voltage that is part of the power supply voltage And a ratio transistor divider to generate on the sense node. The circuit regenerates latching when the rising power supply voltage and the sense node voltage differ by a second predetermined value, preliminary to P-channel threshold voltage or more. The feedback signal disables the flow of current through the power-up reset circuit to substantially eliminate static power consumption at a later time, and the power-up output signal is generated. Circuit provision is incorporated to prevent capacitive coupling from the rising power supply voltage to the critical internal circuit node through the N-well of the P-channel transistor. The first predetermined value of the applied power supply voltage for which the circuit provides the power-up output signal may be formed by adjusting the ratio of the two P-channel transistors.