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Circuit for the ability to test.

机译:电路测试能力。

摘要

PURPOSE:To enhance test efficiency by mounting an input/output means performing initial setting of the memory part within a first main module and reading the data from the memory part and a usual operation means usually operating a common bus control circuit and the memory part. CONSTITUTION:When TMOD is set at a level 1 through a test mode control wire lT and a test mode is set, usual operation is stopped. Next, the common bus control data to an instruction register (IR)1c through a test I/O control wire l1 is set. Subsequently, the address of the memory part 4a or 5a of a reading destination is written in an address register (AR)1d through the control wire l1. Next, SICLK is set at a level 1 through a usual operation control wire lS. By this constitution, the data of the memory part indicated by the address in the AR1d is read in a data register (DR)1e through a common bus 40. Finally, the data of the DR1e is read from the control wire l1.
机译:目的:通过在第一主模块内安装执行存储部分的初始设置并从存储部分读取数据的输入/输出装置和通常操作公共总线控制电路和存储部分的常规操作装置来提高测试效率。组成:当通过测试模式控制线IT将TMOD设置为1级并设置了测试模式时,通常的操作将停止。接下来,设置通过测试I / O控制线l1到指令寄存器(IR)1c的公共总线控制数据。随后,通过控制线11将读取目的地的存储部分4a或5a的地址写入地址寄存器(AR)1d。接下来,通过通常的操作控制线ls将SICLK设置为1级。通过这种构造,由AR1d中的地址表示的存储部分的数据通过公共总线40被读入数据寄存器(DR)1e中。最后,从控制线11中读取DR1e的数据。

著录项

  • 公开/公告号DE69017367T2

    专利类型

  • 公开/公告日1995-07-27

    原文格式PDF

  • 申请/专利权人 TOSHIBA KAWASAKI KK JP;

    申请/专利号DE1990617367T

  • 发明设计人 YAGUCHI TOSHIYUKI US;

    申请日1990-11-26

  • 分类号G06F11/26;G01R31/318;

  • 国家 DE

  • 入库时间 2022-08-22 04:08:12

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