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Field programmable gate array for synchronous and asynchronous operation
Field programmable gate array for synchronous and asynchronous operation
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机译:用于同步和异步操作的现场可编程门阵列
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摘要
A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and operate either to arbitrate the arrival of simultaneous signals or to synchronize simultaneous signals. In addition, each of the RLBs are capable of operating in accordance with two clock signals and an asynchronous initialization. The combination of the RLBs and RABs allow the FPGA to operate synchronously and asynchronously.
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