Asynchronous latch design for field programmable gate arrays

摘要

A programmable logic circuit is provided that solves glitch problems associated with asynchronous logic operations associated with conventional look-up tables by utilizing a preset dominant transparent latch element to replace a conventional look-up table. Since latch elements are normally present in programmable logic circuits (e.g., FPGAs) no additional circuitry is necessary to implement the approach of the present invention. In one exemplary embodiment, an FPGA is provided which includes an array of programmable latch elements, and an array of programmable flip-flop elements generating flip-flop output signals. One or more of the latch elements are programmed to form a preset dominant transparent latch (PDTL) such that the data signals are coupled to the data inputs and preset inputs of the latch. In this manner, the latch operates to replace conventional look-up tables by operating as a primitive OR or NOR gate to generate a desired output.