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Instruction prefetching circuit with a next physical address precalculating circuit

机译:具有下一个物理地址预计算电路的指令预取电路

摘要

After a logical page number is stored, upon execution of a branch instruction, into a logical page number section in an effective address register, an address converting buffer is retrieved in accordance with a value obtained by addition of "1" to a logical page number of an instruction being executed at present, and a physical page number for a page-over is stored into a page-over address register. Thereafter, when a page-over occurs, the output of the page-over address register is selected by a physical page number selecting circuit and stored into the physical page number section in the instruction address register.
机译:在将逻辑页号存储到有效地址寄存器中的逻辑页号部分中之后,在执行分支指令后,根据在逻辑页号上加“ 1”所获得的值来检索地址转换缓冲器。当前正在执行的指令的地址,并将用于翻页的物理页号存储到翻页地址寄存器中。此后,当发生翻页时,翻页地址寄存器的输出由物理页号选择电路选择,并存储到指令地址寄存器中的物理页号部分中。

著录项

  • 公开/公告号US5386521A

    专利类型

  • 公开/公告日1995-01-31

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US19920996177

  • 发明设计人 TAKENORI SAITOH;

    申请日1992-12-23

  • 分类号G06F9/26;G06F9/32;G06F12/10;

  • 国家 US

  • 入库时间 2022-08-22 04:05:31

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