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DMA controller with prefetch cache rechecking in response to memory fetch decision unit's instruction when address comparing unit determines input address and prefetch address coincide
DMA controller with prefetch cache rechecking in response to memory fetch decision unit's instruction when address comparing unit determines input address and prefetch address coincide
A computer which can efficiently perform DMA transfer even if the bus on an input/output adapter side is operating at a high speed and the bus on a main memory side is operating at a low speed. In this computer, the DMA controller functions to prefetch the data to the cache from the main memory and is provided with a prefetch address table holding the prefetch address; an address comparing unit which compares the prefetch address and the input address; a hit recheck control unit which judges if there is a hit in the cache again; and a memory fetch decision unit which instructs the hit recheck control unit to perform a hit recheck when the input address is a cache miss (mis-hit) and a comparison of the input address and the prefetch address shows they coincide while makes a read request to the main memory system when it shows they do not coincide.
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