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Method and system for high-speed virtual-to-physical address translation and cache tag matching
Method and system for high-speed virtual-to-physical address translation and cache tag matching
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机译:高速虚拟地址到物理地址的转换和缓存标签匹配的方法和系统
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摘要
A circuit (100) for high-speed virtual-to-physical address translation and cache tag matching comprises a set-associative memory management unit (112) for producing a first predetermined number, N, of candidate physical address signals (132 and 134), and N candidate address hit signals (150 and 152). A set-associative cache (114) produces a second predetermined number M of address tags (168 and 170) and N-by-M array (M00, M01, M10 and M11) of comparison circuits compare the candidate physical addresses (132 and 134) with address tags (168 and 170) gating by the N address hit signals to generate cache hit signals.
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