Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells

摘要

An array of SONOS memory cells includes: a) a pair of spaced, adjacent SONOS gates atop a silicon substrate within an array area; b) a trench between the gates, the trench having opposing downwardly elongated sidewalls and a base, the sidewalls being doped with a conductivity enhancing impurity of a first conductivity type to define separated source/drain diffusion regions in between and adjacent the respective gates of the pair, the trench being filled with an effectively electrically insulating material; c) a word line commonly interconnecting the adjacent SONOS gates of the pair; and d) separate bit lines separately electrically engaging the separated diffusion regions of the pair. LDD regions are also included. A method of producing such a construction is disclosed.