Extended duration high resolution timer contained in two integrated circuits and having alternating data sequences provided from different integrated circuits

摘要

A computer system provides a 48-bit timer having 120 ns resolution and possessing a rollover period in excess of one year. The preferred embodiment includes two system data buffers (SDBs), each of which includes a full 48-bit timer. The timers are synchronized, and the output of each timer is provided to the host bus in alternating pairs of bits, so that half of the data bits are provided by the first SDB and half of the timer bits are provided by the second SDB. The timer may be read either as a 48-bit timer or a 32-bit timer.