首页> 外国专利> METHOD FOR DYNAMICALLY CHANGING MICROPROCESSOR, CLOCK CONTROL CIRCUIT AND INTERNAL MICROPROCESSOR CLOCK SIGNAL FREQUENCY

METHOD FOR DYNAMICALLY CHANGING MICROPROCESSOR, CLOCK CONTROL CIRCUIT AND INTERNAL MICROPROCESSOR CLOCK SIGNAL FREQUENCY

机译:动态改变微处理机,时钟控制电路和内部微处理机时钟信号频率的方法

摘要

PROBLEM TO BE SOLVED: To provide a clock control system to dynamically change an internal clock frequency of a microprocessor. ;SOLUTION: A clock control system contains a delay sensing circuit 204 which is connected to a clock switching circuit. One pair of tap points is arranged to an output of a delay element which is selected along a delay chain. Each tap point is connected to its own input line of a latching unit through a buffer unit. During an processor operation, an external clock generator gives a clock signal to an input of the delay chain, and the signal is sequentially transferred through each delay element in the delay chain. When a specific rise or fall edge of the clock signal is transferred through the delay chain, corresponded signal transition then appears on the tap point. When high transfer delay is detected, an internal clock frequency is reduced, and when low transfer delay is detected, the internal clock frequency is increased.;COPYRIGHT: (C)1996,JPO
机译:要解决的问题:提供一种时钟控制系统来动态更改微处理器的内部时钟频率。解决方案:时钟控制系统包含延迟感测电路204,该延迟感测电路连接到时钟切换电路。一对抽头点被布置到沿延迟链选择的延迟元件的输出。每个分接点通过缓冲单元连接到其自身的锁存单元的输入线。在处理器操作期间,外部时钟发生器将时钟信号提供给延迟链的输入,并且该信号通过延迟链中的每个延迟元素顺序传输。当时钟信号的特定上升沿或下降沿通过延迟链传输时,相应的信号转换就会出现在抽头点上。当检测到高传输延迟时,将降低内部时钟频率,而当检测到低传输延迟时,则将增加内部时钟频率。; COPYRIGHT:(C)1996,JPO

著录项

  • 公开/公告号JPH08278826A

    专利类型

  • 公开/公告日1996-10-22

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICDS INC;

    申请/专利号JP19950302732

  • 发明设计人 RANDARU PII BIESUTAAFUERUTO;

    申请日1995-11-21

  • 分类号G06F1/04;G06F1/08;G06F15/78;

  • 国家 JP

  • 入库时间 2022-08-22 04:02:55

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