PURPOSE: To correctly output the signal that converges the error of the frequency or phase at a high communication speed by integrating the charge pump output to eliminate the unnecessary high frequency components and securing the necessary information. ;CONSTITUTION: A 4-stage delay circuit 17 is used as a DLL circuit in place of a voltage control oscillator to generate the clocks Φ0 to Φ3 having the phases shifted from each other by a fixed degree to an input clock Φ. Then an integration circuit 15 is connected to the output terminal of a charge pump 12 and an external terminal 23. The delay times of delay circuits DL1 to DL4 of the circuit 17 are controlled by the output of a loop filter 13, and the phase difference between the input clock Φ of the circuit DL1 and the output clock Φ0 of the circuit DL4 is converged to 2π. Then the output charge CH of the pump 12 is integrated by the circuit 15 so that the unnecessary high frequency components included in a PLL loop are eliminated and only the necessary information are outputted. As a result, the parasitic inductance and the capacity of the terminal 23 are reduced and the output waveform distortions are decreased despite a high speed signal DAT.;COPYRIGHT: (C)1996,JPO
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