MEMORY CONTROLLER FOR ACCESS TO MEMORY DEVICES AT DIFFERENT SPEEDS IN DIFFERENT CYCLES

摘要

PROBLEM TO BE SOLVED: To operate memory devices at different speeds in different cycles. ;SOLUTION: This device is provided with a means for receiving address and cycle timing information, and deciding which bank of a DRAM should be accessed, a means for indicating a DRAM format for each bank, a means for storing plural DRAM timing parameters for the part of 6 DRAM cycle for each DRAM format, and a means for deciding the plural DRAM timing parameters suitable to a received address based on the DRAM format indication and the bank decision for each decided bank. The decided plural DRAM timing parameters are received, and the decided bank and address supplies a column, column address, and address strobe to the DRAM according to the decided plural DRAM timing parameters for the specific bank.;COPYRIGHT: (C)1996,JPO