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shindoro - mu generation circuit

机译:是你Doro - 木generation circuit

摘要

PURPOSE:To reduce the circuit scale used for an optical card, a magnetooptical disk, a DAT, by multiplying an output of an EXOR circuit by alpha (m) times and latching each output thereof the a register by different clocks, in an encoding/decoding circuit in a field for correcting an error. CONSTITUTION:Syndromes S0-S3 are constituted of a bus line, and a clock CK and an OE (output enable) are used so as to complete with each other among the syndromes S0-S3. Therefore, the clock and the OE used for each of the syndromes S0-S3 are controlled by a signal shown in the figure. The clocks CKB1, 3, 5 and 7 are inversion signals H L and L H of CK1, 3, 5 and 7. In this way, as for an input J, it is necessary to input it in synchronism with the clock CK1 at every ji. Also, SCL is a signal which becomes L, when a first receiving word j1 is inputted. In this way, in a syndrome S, its S0-S3 are outputted at every four periods, and at every SCL, the final answer is generated.
机译:目的:通过将EXOR电路的输出乘以alpha(m)倍,并使用不同的时钟将其每个输出锁存到一个寄存器中,以减少光卡,磁光盘,DAT的电路规模,场中的用于纠错的解码电路。组成:综合症S0-S3由一条总线组成,并且使用了时钟CK和OE(输出使能),以便在综合症S0-S3之间相互完善。因此,用于每个校正子S0-S3的时钟和OE由图中所示的信号控制。时钟CKB1、3、5和7是CK1、3、5和7的反相信号H L和L H。以这种方式,对于输入J,必须在每个ji上与时钟CK1同步地输入它。而且,当输入第一接收字j1时,SCL是变为L的信号。这样,在校正子S中,每四个周期输出一次S0-S3,并在每个SCL处生成最终答案。

著录项

  • 公开/公告号JP2541938B2

    专利类型

  • 公开/公告日1996-10-09

    原文格式PDF

  • 申请/专利权人 CANON KK;

    申请/专利号JP19860232001

  • 发明设计人 IWAMURA KEIICHI;

    申请日1986-09-30

  • 分类号H03M13/00;

  • 国家 JP

  • 入库时间 2022-08-22 03:57:50

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