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Method of measuring the trap level concentration of polycrystalline grain boundaries

机译:测量多晶晶界的陷阱能级浓度的方法

摘要

PURPOSE:To make it possible to measure the trap level density of a polycrystal grain boundary by a method wherein an electrostatic capacity per unit area of an insulation film, temperature, and the inclination of gate voltage characteristics to the drain current in a subthreshold area are determined and a calculation is made on the basis of a specific equation regarding these physical quantities. CONSTITUTION:In an insulation gate field effect type transistor with a polycrystal semiconductor having a permittivity of epsilons(F/cm) as a substrate material, an electrostatic capacity Ci(F/cm2) per unit area of an insulation film, temperature T(K), and the inclination S(V/column) of gate voltage characteristics to the drain current of a subthreshold area are specifically determined. A calculation is made using equation I on the basis of physical quantities Ci, T and S and the trap level density (piece/V/cm2) of a grain boundary area is measured. This makes it possible to measure the trap level density of a polycrystal grain boundary area.
机译:目的:通过以下方法可以测量多晶晶界的陷阱能级密度:绝缘膜每单位面积的静电电容,温度以及栅极电压特性对亚阈值区域中漏极电流的倾斜度为:确定并根据有关这些物理量的特定公式进行计算。组成:在一个以ε(F / cm)介电常数的多晶半导体为衬底材料的绝缘栅场效应型晶体管中,绝缘膜每单位面积的静电电容Ci(F / cm 2),温度具体地,确定T(K)和栅极电压特性相对于亚阈值区域的漏极电流的倾斜度S(V /列)。基于物理量Ci,T和S使用等式I进行计算,并且测量晶界区域的陷阱能级密度(件/ V / cm 2)。这使得可以测量多晶粒边界区域的陷阱能级密度。

著录项

  • 公开/公告号JP2504134B2

    专利类型

  • 公开/公告日1996-06-05

    原文格式PDF

  • 申请/专利权人 NIPPON ELECTRIC CO;

    申请/专利号JP19880226492

  • 发明设计人 HAYAMA HIROSHI;

    申请日1988-09-12

  • 分类号H01L29/786;H01L21/66;

  • 国家 JP

  • 入库时间 2022-08-22 03:56:18

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