Low energy differential logic gate circuitry having substantially invariant clock signal loading

摘要

An energy efficient logic gate circuit (11,12) design that provides a substantially constant load to a clock source (Φ1, Φ2) regardless of logic signal inputs (IN1 - IN¯1 IN2 - IN¯2) to, or outputs from, the gate. The gate provides two complementary outputs (OUT1,OUT¯1, OUT2,OUT¯2) and utilizes cross-coupled transistors (17,18) to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two logic blocks (15,16), each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes (26,27) for recharging the outputs of the gate, present the constant load to the clock source.