Clamping circuit for clamping clock signal in low state in electronic installation, has output logic gate including input connected to charging capacitors for receiving information representative of voltage at its terminals

摘要

The circuit (14) has an inlet (16) for receiving a clock signal from a clock (12), and an outlet (18) for supplying the clock signal. Charge circuits (44, 46) include capacitors (48, 50) connected to the inlet through charge branches (52, 54) for charging the capacitors and discharge branches (56, 58) for discharging the capacitors, where discharging of the capacitors is slower than charging. An output logic gate (20) includes an output connected to the outlet, and an input connected to the charging capacitors for receiving information representative of the voltage at its terminals.