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Simulation by emulating level sensitive latches with edge trigger latches
Simulation by emulating level sensitive latches with edge trigger latches
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机译:通过使用边沿触发锁存器仿真电平敏感锁存器进行仿真
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摘要
A hardware simulation system is disclosed which includes a high frequency clock which is gated with a system clock to produce a high frequency enabled clock. The high frequency enabled clock is used to clock an edge triggered latch within the hardware simulation system. Thus, the system advantageously emulates level sensitive latches using edge triggered latches.
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