The present invention is not limited to the use of positive logic functions and is directed to a domino logic implementation using logic cells 200, 300 that may be implemented using the MOS technology. A major feature of the present invention is the use of a single clock cycle (PHI1) to provide a separate clock phase (PHI1, PHI2) for a second function, such as a sum function of a first function and a full adder logic cell, PHI1d). The separated clock phase that freezes and closes the second function corresponds to a delayed clock phase that opens and closes the first function, where the clock delay corresponds to the delay through the first function. In one embodiment, the delay can be made equal to the delay of the first function by using the same circuit as the delay circuit of the first function to generate the delay.
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