CIRCUIT FOR REDUCING TRANSIENT SIMULTANEOUS CONDUCTION A circuit that reduces transient simultaneous conduction.

摘要

Up circuit for minimizing the simultaneous conduction through the pull-up transistors PB3 and NB3 of the buffer circuit. One high-potential power rail (V_CCA) From the other high-potential power rail (V_CCB) And the potentials of the two high potential rails are not the same, the transient eliminating circuit (20) is arranged so that the translators are connected in parallel to each other Any static current (I_CCT) Connected between the input and output stages in such a way that they can be used without. The over-subtraction circuit minimizes the simultaneous conduction through the pull-up and p-down transistors PB3 and NB3 of the translator by delaying the turn-on of the pull-down transistor NB3 until the pull-up transistor PB3 is completely turned off. This controls the PMOS transistor PB4 used to control the pull-down transistor NB3 by connecting an NMOS transistor NB4 to the output of the translator circuit. By using the NMOS transistor as an initial pull-down on the output, In a preferred embodiment of the invention. The second NMOS transistor NB5 of the over-subtraction circuit also functions to control the pull-down transistor by operating in an inverted mode of the first NMOS transistor so that the NMOS transistor is completely turned off if necessary.