CIRCUIT FOR REDUCING TRANSIENT SIMULTANEOUS CONDUCTION

摘要

A transient-eliminating circuit for minimizing simultaneous conduction through the pull-up and pull-down transistors (PB3, NB3) of a buffer circuit. In a buffer circuit used to translate logic signals from circuits supplied by one high-potential power rail (VCCA) to circuits supplied by another high-potential power rail (VCCB), in which the potentials of the two high-potential rails are not equal, the transient-eliminating circuit (20) is coupled between the output stage and the input stage in such a way that the translator can be utilized independent of power-up sequencing and without any static current ICCt. The transient-eliminating circuit minimizes simultaneous conduction through the pull-up and pull-down transistors (PB3, NB3) of the translator by delaying the turn-on of the pull-down transistor (NB3) until the pull-up transistor (PB3) is completely off. This is achieved in the preferred embodiment of the invention by coupling an NMOS transistor (NB4) to the output of the translator circuit to act as an early pull-down on the output by using that NMOS transistor to control a PMOS transistor (PB4) which is in turn used to control the pull-down transistor (NB3). A second NMOS transistor (NB5) of the transient-eliminating circuit also acts to control the pull-down transistor by operating in the reverse mode of the first NMOS transistor so as to ensure that the NMOS transistor is completely off when required.