High speed divider for performing hexadecimal division having control circuit for generating different division cycle signals to control circuit in performing specific functions

摘要

A divider comprising a first and second normalizing circuits (5, 6) each which holds a hexadecimal-normalized mantissa data of a dividend and divisor respectively, a selector (7) which inputs the mantissa outputted from the first normalizing circuit (5), a remainder data outputted from a latch (13), a borrow signal (16) of a subtracter (8) which subtracts the mantissa data of the divisor from the mantissa of the dividend data of the remainder data, and control signals 21, 22, 23 respectively indicating a first, second and third and after third division cycles, through-outputs the mantissa data of the dividend in the first division cycle, shifts the mantissa data outputted from the first normalizing circuit (5) to the right by three bits and outputs it when the borrow signal (16) indicates "0" in the second division cycle, shifts the mantissa data outputted from the first normalizing circuit (5) to the left by one bit when the borrow signal (16) indicates "1", and through- outputs the remainder data outputted from the latch (13) in the third division cycle, and a dividing circuit. (100) which calculates a quotient data and a remainder data by using data outputted from the selector (7) and the mantissa data outputted from the second normalizing circuit (6).