首页> 外国专利> Vertical type semiconductor device provided with an improved construction to greatly decrease device on-resistance without impairing breakdown

Vertical type semiconductor device provided with an improved construction to greatly decrease device on-resistance without impairing breakdown

机译:垂直型半导体器件具有改进的结构,以在不损害击穿的情况下大大降低器件的导通电阻

摘要

A vertical type semiconductor device is provided with an improved construction which greatly decreases the on-resistance without impairing the breakdown voltage thereof. In the fundamental DMOS cells that control a current to constitute the vertical semiconductor device, through-hole cells are arranged along the sides of a cell having a channel. The through-hole cell includes a through-hole extending from the surface of an n.sup.- -type drift region toward an n.sup.+ -type drain region, and also includes an n.sup.+ -type through-hole region that is formed by diffusing impurities from the inner wall of the through-hole which is continuous with the n.sup.+ -type drain region. A breakdown voltage of the element is maintained by the n.sup.- -type drift region between a p- type well region and the n.sup.+ -type through-hole region or the n.sup.+ -type drain region. Given the unique arrangement of the through-hole cells, the JFET resistance component becomes negligibly small between the DMOS cells neighboring along the sides of the cells despite the fact that the cells are finely formed, and a small on- resistance is exhibited.
机译:垂直型半导体器件具有改进的结构,该结构在不损害其击穿电压的情况下大大减小了导通电阻。在控制电流以构成垂直半导体器件的基本DMOS单元中,沿具有沟道的单元的侧面布置通孔单元。所述通孔单元包括从n-型漂移区的表面向n-型漏极区域延伸的通孔,并且还包括n +型通孔。通过从通孔的内壁扩散杂质而形成的孔区域,该孔区域与n +型漏极区域连续。元件的击穿电压通过p型阱区域与n +型通孔区域或n +型漏极区域之间的n-型漂移区域来维持。 。考虑到通孔单元的独特布置,尽管单元细密地形成,但JFET电阻分量在沿单元侧面相邻的DMOS单元之间很小,可以忽略不计,并且导通电阻很小。

著录项

  • 公开/公告号US5504360A

    专利类型

  • 公开/公告日1996-04-02

    原文格式PDF

  • 申请/专利权人 NIPPONDENSO CO. LTD.;

    申请/专利号US19940293421

  • 发明设计人 KUNIHIKO HARA;NORIHITO TOKURA;

    申请日1994-08-22

  • 分类号H01L29/76;H01L29/94;H01L31/062;

  • 国家 US

  • 入库时间 2022-08-22 03:38:49

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