Memory apparatus including a shift circuit for shifting a word select signal by a predetermined number of words

摘要

A memory apparatus and a data processor using the same, wherein a shift circuit 12 which shifts a word select signal generated by an address decoder 11 by a predetermined number of words and gives it to a memory when a predetermined signal is given from the outside, is included, and the word select signal, which is a decoded address signal inputted from the outside, is given intact to the memory when the predetermined signal is not given to the shift circuit 12, and the word select signal is shifted and given to the memory when the predetermined signal is given to the shift circuit 12, so that the word different word addresses are accessed when the same address signal is given, thereby the word contiguous to the inputted address can be accessed with a simple configuration and a small amount of hardwares and by restraining increase of power consumption.