Semiconductor memory device with error self-correction system starting parity bit generation/error correction sequences only when increase of error rate is forecasted

摘要

A semiconductor memory device has a built-in error correction system for correcting undesirably inverted data bits, and the built-in error correction system starts a parity bit generating sequence and an error correcting sequence only when increase of error rate is forecasted, thereby increasing the access speed without sacrifice of the reliability.