INSPECTION FACILITATION DESIGN METHOD FOR ROUTE DELAY FAULT AND INSPECTION SYSTEM GENERATION METHOD

摘要

PROBLEM TO BE SOLVED: To provide an inspection facilitation design method for a route delay fault, which can obtain a high fault detection rate without considerably increasing area overhead. ;SOLUTION: The unprocessed route delay fault which is given in an integrated circuit is selected (S11). An initial pattern is generated for the selected route delay fault (S12), and logic values which are set in respective scan flip flops are stored (S13). A transition pattern is generated for the selected route delay fault (S14). It is judged whether the scan flip flop where the logic value is contradicted between the initial pattern and the transition pattern exists or not (S15). A D latch is inserted into the output signal line of the scan flip flop whose logic value is contradicted (S16). The contradiction of the logic value is dissolved by the D latch and the inspection of the route delay fault becomes easy.;COPYRIGHT: (C)1997,JPO