首页> 外国专利> MANUFACTURE OF SEMICONDUCTOR DEVICE, MANUFACTURE OF INSULATED GATE SEMICONDUCTOR DEVICE, AND INSULATED GATE SEMICONDUCTOR DEVICE

MANUFACTURE OF SEMICONDUCTOR DEVICE, MANUFACTURE OF INSULATED GATE SEMICONDUCTOR DEVICE, AND INSULATED GATE SEMICONDUCTOR DEVICE

机译:半导体装置的制造,绝缘栅型半导体装置的制造以及绝缘栅型半导体装置

摘要

PROBLEM TO BE SOLVED: To form a source contact region in a self-matching manner without using photolithography, and realize a high level of integration. ;SOLUTION: By using a first film 12 which was used for forming a trench, a second film 14 covering the trench surface is formed. By etching back the whole surfaces of the first film 12 and the second film 14, and using the difference of the etching rate, only the first film 12 is eliminated, and a contact hole is automatically formed adjacently to the trench. Since the contact hole is formed in an self-matching manner, working precision of the minimum pattern size in photolithography can be realized. As to the second film 14, sufficient film thickness for functioning as an interlayer insulating film can be ensured. The first film 12 and the second film 14 are positioned above the semiconductor substrate surface, so that the stress at the time of film formation and its working is not applied to the semiconductor substrate.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:在不使用光刻的情况下以自匹配的方式形成源极接触区,并实现高集成度。 ;解决方案:通过使用用于形成沟槽的第一膜12,形成覆盖沟槽表面的第二膜14。通过回蚀第一膜12和第二膜14的整个表面,并利用蚀刻速率的差异,仅去除第一膜12,并在沟槽附近自动形成接触孔。由于以自匹配的方式形成接触孔,所以可以实现光刻中的最小图案尺寸的加工精度。对于第二膜14,可以确保足够的膜厚度以用作层间绝缘膜。第一膜12和第二膜14位于半导体衬底表面上方,从而在膜形成及其加工时的应力不施加到半导体衬底上。;版权所有:(C)1997,JPO

著录项

  • 公开/公告号JPH09129877A

    专利类型

  • 公开/公告日1997-05-16

    原文格式PDF

  • 申请/专利权人 TOYOTA CENTRAL RES & DEV LAB INC;

    申请/专利号JP19950305066

  • 发明设计人 UESUGI TSUTOMU;SUZUKI TAKASHI;

    申请日1995-10-30

  • 分类号H01L29/78;H01L21/306;H01L21/336;

  • 国家 JP

  • 入库时间 2022-08-22 03:36:19

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号