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HIGH SPEED VARIABLE LENGTH CODE DECODER AND HIGH SPEED VARIABLE LENGTH CODE DECODING METHOD

机译:高速可变长度码译码器和高速可变长度码译码方法

摘要

PROBLEM TO BE SOLVED: To decode two codes for each cycle and to attain effective high speed processing by storing received serial data to two latch circuits and using two barrel shifters so as to generate a window output sequence. ;SOLUTION: Serial data given to a buffer memory 50 are outputted to latch circuits 101, 102 based on a control signal READ, a CARRY signal and a clock signal CLK. Then the data in a buffer memory 50 and the latch circuits are given to a 1st barrel shifter 103 by the CARRY and a 1st window output sequence 117 is generated. The 2nd barrel shifter 104 receives an output sequence of the sequence 117 and an output sequence of a relay circuit 105 and provides an output of a 2nd window output sequence by the control of the memory device 200. Since two codes are decoded for each cycle by an adder 310 of an accumulation block 300, two latch circuits 320, 330 and an MUX 340, the configuration is simplifier and high speed processing is conducted effectively.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:每个周期解码两个代码,并通过将接收到的串行数据存储到两个锁存电路并使用两个桶形移位器来生成窗口输出序列,以实现有效的高速处理。解决方案:提供给缓冲存储器50的串行数据基于控制信号READ,CARRY信号和时钟信号CLK输出到锁存电路101、102。然后,通过CARRY将缓冲存储器50和锁存电路中的数据提供给第一桶形移位器103,并生成第一窗口输出序列117。第二桶形移位器104接收序列117的输出序列和中继电路105的输出序列,并通过存储装置200的控制来提供第二窗口输出序列的输出。累加块300的加法器310,两个锁存电路320、330和MUX 340,简化了结构并有效地进行了高速处理。版权所有:(C)1997,日本特许厅

著录项

  • 公开/公告号JPH09130266A

    专利类型

  • 公开/公告日1997-05-16

    原文格式PDF

  • 申请/专利权人 DAEWOO ELECTRON CO LTD;

    申请/专利号JP19960250987

  • 发明设计人 SON EISEKI;

    申请日1996-09-02

  • 分类号H03M7/42;

  • 国家 JP

  • 入库时间 2022-08-22 03:36:17

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