LIMIT-VOLTAGE AUTOMATIC VERIFYING CIRCUIT FOR NONVOLATILE MEMORY CELL AND CONFIRMING METHOD FOR PROGRAM AND ERASING STATE OF NONVOLATILE MEMORY CELL UTILIZING THE AUTOMATIC VERIFYING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To shorten a program and an erasing time by automatically verifying limit voltage in response to the change of the quantity of charges injected to the floating gate terminal of a nonvolatile memory cell at the time of the program and erasing time of the cell. ;SOLUTION: The supply means of a cell program or bias voltage for erasing and a logical signal by a drain current are generated at a gate and drain and source terminals in a limit-voltage automatic verifying circuit for a cell while the automatic verifying circuit is composed of an inverter 11, by which the limit voltage of an input logic and the limit voltage of the cell are equalized. When the limit voltage of the input logic of the inverter is equalized to drain voltage, an output from the inverter is inverted, and an instant when the cell is programmed at a desired limit-voltage level can be verified automatically. Since even the time of an erasing mode is composed similarly at the time of the program, a desired erased state can be obtained.;COPYRIGHT: (C)1996,JPO