A CACHE FLUSH MECHANISM FOR A SECONDARY CACHE MEMORY

摘要

An effective mechanism for cache flushing that can be applied to a memory system operated in dual-mode is disclosed. The dual-mode is composed of two modes using two physically distinguished main memory space respectively at a common logical address in at least a portion of whole address. The interruption of the signal (SMIACT#) that represents the switching of the mode by secondary cache is provided. When SMIACT# is generated by CPU and it is detected by the system core, the system core switches the memory bank for the cache memory to write back, resulting into violating memory consistency between the cache and main memory. But this invention just interrupts the SMIACT# to reach to the system core before the cache flushing is over, assuring the content of the cache memory to be written back to a correct memory bank where the data originally resided, since the system core believes that the mode has not yet been switched though the CPU actually generated SMIACT#.