A CACHE FLUSH MECHANISM FOR A SECONDARY CACHE MEMORY

摘要

An effective cache flush method that can be applied to a memory system operating in dual mode is disclosed. The dual mode consists of two modes that are physically separated and each use two main memory spaces at at least some common logical address of the full address. An interrupt of the signal SMIACT # indicating the switch of the mode by the second cache is provided. When the CPU generates SMIACT # and the system core detects it, the system core switches the memory bank to cache memory to write back, which breaks the memory match between cache and main memory. However, the present invention immediately interrupts SMIACT # reaching the system core before flushing the cache is finished, because the system core believes that the mode is not yet switched even though the CPU actually generated SMIACT #. The data will be written back to the correct memory bank in which it resided.