首页>
外国专利>
Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions
Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions
展开▼
机译:用于在优化编译器中进行指令调度以最小化开销指令的方法和装置
展开▼
页面导航
摘要
著录项
相似文献
摘要
Apparatus and methods are disclosed for scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modem microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units. They also have the ability to add two values to form the address within memory load and store instructions. In such microprocessors this invention can, where applicable, accelerate the execution of modulo-scheduled loops. The invention consists of a technique to achieve this speed up by systematically reducing the number of certain overhead instructions in modulo scheduled loops. The technique involves identifying reducible overhead instructions, scheduling the balance of the instructions with normal modulo scheduling procedures and then judiciously inserting no more than three copies of the reducible instructions into the schedule.
展开▼